"FDSTDL: Low-power technique for FinFET domino circuits."

Sandeep Garg, Tarun Kumar Gupta (2019)

> Home

Details and statistics

DOI: 10.1002/CTA.2627

access: closed

type: Journal Article

metadata version: 2021-10-14

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/ijcta/GargG19
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/ijcta/GargG19
Sandeep Garg, Tarun Kumar Gupta:
FDSTDL: Low-power technique for FinFET domino circuits. Int. J. Circuit Theory Appl. 47(6): 917-940 (2019)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.