"Highly resilient 17-level fault-tolerant multilevel inverter topology with ..."

Anilkumar Chappa et al. (2024)

> Home

Details and statistics

DOI: 10.1002/CTA.3876

access: closed

type: Journal Article

metadata version: 2024-06-18

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/ijcta/ChappaGSGC24
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/ijcta/ChappaGSGC24
Anilkumar Chappa, Shubhrata Gupta, Lalit Kumar Sahu, Krishna Kumar Gupta, Allamsetty Hema Chander:
Highly resilient 17-level fault-tolerant multilevel inverter topology with reduced capacitor size. Int. J. Circuit Theory Appl. 52(6): 2803-2822 (2024)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.