Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID"Power-aware high level evaluation model of interconnect length of on-chip ..."
Xiaojun Wang et al. (2018)
- Xiaojun Wang, Feng Shi, Yizhuo Wang, Hong Zhang, Xu Chen, Wen-Fei Fu:
Power-aware high level evaluation model of interconnect length of on-chip memory network topology. Int. J. Comput. Sci. Eng. 17(4): 422-431 (2018)
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-05-03 16:21 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
