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"Design and simulation of logic gates using single electron transistors at ..."

Aranggan Venkataratnam, Ashok K. Goel (2006)

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DOI: 10.1504/IJCSE.2006.012770

access: closed

type: Journal Article

metadata version: 2020-07-30

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Aranggan Venkataratnam, Ashok K. Goel:
Design and simulation of logic gates using single electron transistors at room temperature. Int. J. Comput. Sci. Eng. 2(3/4): 179-188 (2006)

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