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"Low-power enhanced system-on-chip design for sequential minimal ..."

Chih-Hsiang Peng et al. (2015)

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DOI: 10.1049/IET-CDT.2013.0153

access: closed

type: Journal Article

metadata version: 2020-07-14

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Chih-Hsiang Peng, Po-Chuan Lin, Shovan Barma, Jhing-Fa Wang, Hong-Yuan Peng, K. Bharanitharan, Ta-Wen Kuan:
Low-power enhanced system-on-chip design for sequential minimal optimisation learning core with tri-layer bus and butterfly-path accelerator. IET Comput. Digit. Tech. 9(2): 93-100 (2015)

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