"1.2-V, 10-bit, 60-360 MS/s time-interleaved pipelined analog-to-digital ..."

Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins (2010)

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DOI: 10.1049/IET-CDS.2008.0229

access: closed

type: Journal Article

metadata version: 2020-09-10

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Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
1.2-V, 10-bit, 60-360 MS/s time-interleaved pipelined analog-to-digital converter in 0.18 μm CMOS with minimised supply headroom. IET Circuits Devices Syst. 4(1): 1-13 (2010)

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