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ORCID"Bit-parallel systolic multiplier over GF ( 2 m ) for irreducible ..."
Sudha Ellison Mathe, Lakshmi Boppana (2018)
- Sudha Ellison Mathe
, Lakshmi Boppana:
Bit-parallel systolic multiplier over GF ( 2 m ) for irreducible trinomials with ASIC and FPGA implementations. IET Circuits Devices Syst. 12(4): 315-325 (2018)
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