"Circuit-level design technique to mitigate impact of process, voltage and ..."

Vishesh Dokania, Aminul Islam (2015)

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DOI: 10.1049/IET-CDS.2014.0167

access: closed

type: Journal Article

metadata version: 2021-01-27

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Vishesh Dokania, Aminul Islam:
Circuit-level design technique to mitigate impact of process, voltage and temperature variations in complementary metal-oxide semiconductor full adder cells. IET Circuits Devices Syst. 9(3): 204-212 (2015)

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