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"Power profiling-guided floorplanner for 3D multi-processor systems-on-chip."

Ignacio Arnaldo et al. (2012)

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DOI: 10.1049/IET-CDS.2011.0350

access: closed

type: Journal Article

metadata version: 2022-10-02

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  - https://dblp.org/rec/journals/iet-cds/ArnaldoRAH12
Ignacio Arnaldo, José Luis Risco-Martín, José Luis Ayala, José Ignacio Hidalgo:
Power profiling-guided floorplanner for 3D multi-processor systems-on-chip. IET Circuits Devices Syst. 6(5): 322-329 (2012)

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