"High-Parallelism and Pipelined Architecture for Accelerating Sort-Merge ..."

Meiting Xue et al. (2024)

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DOI: 10.1587/TRANSFUN.2023EAP1135

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type: Journal Article

metadata version: 2024-10-15

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Meiting Xue, Wenqi Wu, Jinfeng Luo, Yixuan Zhang, Bei Zhao:
High-Parallelism and Pipelined Architecture for Accelerating Sort-Merge Join on FPGA. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107(10): 1582-1594 (2024)

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