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"Simple Design Formula for Parallel Plate Mode Suppression by Ground ..."

Takeshi Yuasa, Tamotsu Nishino, Hideyuki Oh-Hashi (2005)

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DOI: 10.1093/IETELE/E88-C.7.1401

access: closed

type: Journal Article

metadata version: 2020-04-11

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  - https://dblp.org/rec/journals/ieicet/YuasaNO05
Takeshi Yuasa, Tamotsu Nishino, Hideyuki Oh-Hashi:
Simple Design Formula for Parallel Plate Mode Suppression by Ground Via-Holes in Multi-Layered Packages. IEICE Trans. Electron. 88-C(7): 1401-1405 (2005)

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