"A 1R/1W SRAM Cell Design to Keep Cell Current and Area Saving against ..."

Hiroyuki Yamauchi, Toshikazu Suzuki, Yoshinobu Yamagami (2007)

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DOI: 10.1093/IETELE/E90-C.4.749

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type: Journal Article

metadata version: 2024-02-05

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Hiroyuki Yamauchi, Toshikazu Suzuki, Yoshinobu Yamagami:
A 1R/1W SRAM Cell Design to Keep Cell Current and Area Saving against Simultaneous Read/Write Disturbed Accesses. IEICE Trans. Electron. 90-C(4): 749-757 (2007)

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