"Coding Floorplans with Fewer Bits."

Katsuhisa Yamanaka, Shin-Ichi Nakano (2006)

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DOI: 10.1093/IETFEC/E89-A.5.1181

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type: Journal Article

metadata version: 2020-04-11

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Katsuhisa Yamanaka, Shin-Ichi Nakano:
Coding Floorplans with Fewer Bits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(5): 1181-1185 (2006)

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