"Reducing Consuming Clock Power Optimization of a 90 nm Embedded Processor ..."

Tetsuya Yamada et al. (2006)

> Home

Details and statistics

DOI: 10.1093/IETELE/E89-C.3.287

access: closed

type: Journal Article

metadata version: 2020-04-11

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/ieicet/YamadaANOKIOTANH06
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/ieicet/YamadaANOKIOTANH06
Tetsuya Yamada, Masahide Abe, Yusuke Nitta, Kenji Ogura, Manabu Kusaoke, Makoto Ishikawa, Motokazu Ozawa, Kiwamu Takada, Fumio Arakawa, Osamu Nishii, Toshihiro Hattori:
Reducing Consuming Clock Power Optimization of a 90 nm Embedded Processor Core. IEICE Trans. Electron. 89-C(3): 287-294 (2006)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.