"All Digital Dividing Ratio Changeable PLL Using Delay Clock Pulse with Low ..."

Mitsutoshi Yahara et al. (2006)

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DOI: 10.1093/IETFEC/E89-A.6.1527

access: closed

type: Journal Article

metadata version: 2020-04-11

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Mitsutoshi Yahara, Kuniaki Fujimoto, Hirofumi Sasaki, Takashi Shibuya, Yoshinori Higashi:
All Digital Dividing Ratio Changeable PLL Using Delay Clock Pulse with Low Jitter. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(6): 1527-1532 (2006)

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