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"Heuristic Sizing Methodology for Designing High-Performance CMOS Level ..."

Jinn-Shyan Wang, Yu-Juey Chang, Chingwei Yeh (2010)

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DOI: 10.1587/TRANSELE.E93.C.1540

access: closed

type: Journal Article

metadata version: 2020-04-11

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  - https://dblp.org/rec/journals/ieicet/WangCY10
Jinn-Shyan Wang, Yu-Juey Chang, Chingwei Yeh:
Heuristic Sizing Methodology for Designing High-Performance CMOS Level Converters with Balanced Rise and Fall Delays. IEICE Trans. Electron. 93-C(10): 1540-1543 (2010)

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