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"Design of 65 nm Sub-Threshold SRAM Using the Bitline Leakage Prediction ..."

Jinn-Shyan Wang, Pei-Yao Chang, Chi-Chang Lin (2012)

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DOI: 10.1587/TRANSELE.E95.C.172

access: closed

type: Journal Article

metadata version: 2020-04-11

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  dblp key:
  - journals/ieicet/WangCL12
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  persistent URL:
  - https://dblp.org/rec/journals/ieicet/WangCL12
Jinn-Shyan Wang, Pei-Yao Chang, Chi-Chang Lin:
Design of 65 nm Sub-Threshold SRAM Using the Bitline Leakage Prediction Scheme and the Non-trimmed Sense Amplifier. IEICE Trans. Electron. 95-C(1): 172-175 (2012)

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