"A New 1.25-Gb/s Burst Mode Clock and Data Recovery Circuit Using Two ..."

Chang-Kyung Seong, Seung-Woo Lee, Woo-Young Choi (2008)

> Home

Details and statistics

DOI: 10.1093/IETCOM/E91-B.5.1397

access: closed

type: Journal Article

metadata version: 2020-04-11

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/ieicet/SeongLC08
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/ieicet/SeongLC08
Chang-Kyung Seong, Seung-Woo Lee, Woo-Young Choi:
A New 1.25-Gb/s Burst Mode Clock and Data Recovery Circuit Using Two Digital Phase Aligners and a Phase Interpolator. IEICE Trans. Commun. 91-B(5): 1397-1402 (2008)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.