"A Digitally Assisted Gain and Offset Error Cancellation Technique for a ..."

Hiroki Sakurai, Shigeto Tanaka, Yasuhiro Sugimoto (2007)

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DOI: 10.1093/IETFEC/E90-A.10.2272

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type: Journal Article

metadata version: 2020-04-11

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Hiroki Sakurai, Shigeto Tanaka, Yasuhiro Sugimoto:
A Digitally Assisted Gain and Offset Error Cancellation Technique for a CMOS Pipelined ADC with a 1.5-bit Bit-Block Architecture. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(10): 2272-2279 (2007)

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