"A Low-Power Mixed-Architecture ADC with Time-Interleaved Correlated Double ..."

Jin-Fu Lin, Soon-Jyh Chang (2011)

> Home

Details and statistics

DOI: 10.1587/TRANSELE.E94.C.89

access: closed

type: Journal Article

metadata version: 2020-04-11

- view
  authority control:
- export record
  dblp key:
  - journals/ieicet/LinC11
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/ieicet/LinC11
Jin-Fu Lin, Soon-Jyh Chang:
A Low-Power Mixed-Architecture ADC with Time-Interleaved Correlated Double Sampling Technique and Power-Efficient Back-End Stages. IEICE Trans. Electron. 94-C(1): 89-101 (2011)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.