Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"A Fast Gate-Level Register Relocation Method for Circuit Size Reduction in ..."

Yukihide Kohira, Atsushi Takahashi (2008)

> Home

Details and statistics

DOI: 10.1093/IETFEC/E91-A.10.3030

access: closed

type: Journal Article

metadata version: 2023-05-01

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/ieicet/KohiraT08
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/ieicet/KohiraT08
Yukihide Kohira, Atsushi Takahashi:
A Fast Gate-Level Register Relocation Method for Circuit Size Reduction in General-Synchronous Framework. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(10): 3030-3037 (2008)

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.