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"Gate-Level Register Relocation in Generalized Synchronous Framework for ..."

Yukihide Kohira, Atsushi Takahashi (2007)

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DOI: 10.1093/IETFEC/E90-A.4.800

access: closed

type: Journal Article

metadata version: 2023-05-01

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Yukihide Kohira, Atsushi Takahashi:
Gate-Level Register Relocation in Generalized Synchronous Framework for Clock Period Minimization. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(4): 800-807 (2007)

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