"An FPGA Implementation for a Flexible-Length-Arithmetic Processor ..."

Tatsuya Kawamoto et al. (2016)

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DOI: 10.1587/TRANSINF.2016PAP0029

access: closed

type: Journal Article

metadata version: 2023-11-12

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Tatsuya Kawamoto, Xin Zhou, Jacir Luiz Bordim, Yasuaki Ito, Koji Nakano:
An FPGA Implementation for a Flexible-Length-Arithmetic Processor Employing the FDFM Processor Core Approach. IEICE Trans. Inf. Syst. 99-D(12): 2901-2910 (2016)

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