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"Design and Verification of On-Chip Impedance-Matching Circuit Using ..."

Haruichi Kanaya et al. (2006)

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DOI: 10.1093/IETELE/E89-C.12.1888

access: closed

type: Journal Article

metadata version: 2020-04-11

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  - https://dblp.org/rec/journals/ieicet/KanayaPKY06
Haruichi Kanaya, Ramesh K. Pokharel, Fuminori Koga, Keiji Yoshida:
Design and Verification of On-Chip Impedance-Matching Circuit Using Transmission-Line Theory for 2.4 GHz-Band Wireless Receiver Front-End. IEICE Trans. Electron. 89-C(12): 1888-1895 (2006)

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