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"A Verification-Aware Design Methodology for Thread Pipelining Parallelization."

Guo-An Jian et al. (2012)

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DOI: 10.1587/TRANSINF.E95.D.2505

access: closed

type: Journal Article

metadata version: 2020-04-11

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  dblp key:
  - journals/ieicet/JianCCG12
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  persistent URL:
  - https://dblp.org/rec/journals/ieicet/JianCCG12
Guo-An Jian, Cheng-An Chien, Peng-Sheng Chen, Jiun-In Guo:
A Verification-Aware Design Methodology for Thread Pipelining Parallelization. IEICE Trans. Inf. Syst. 95-D(10): 2505-2513 (2012)

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