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"Evaluating Energy-Efficiency of DRAM Channel Interleaving Schemes for ..."

Satoshi Imamura et al. (2018)

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DOI: 10.1587/TRANSINF.2017EDP7296

access: closed

type: Journal Article

metadata version: 2022-10-02

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  - https://dblp.org/rec/journals/ieicet/ImamuraYIOSF18
Satoshi Imamura, Yuichiro Yasui, Koji Inoue, Takatsugu Ono, Hiroshi Sasaki, Katsuki Fujisawa:
Evaluating Energy-Efficiency of DRAM Channel Interleaving Schemes for Multithreaded Programs. IEICE Trans. Inf. Syst. 101-D(9): 2247-2257 (2018)

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