"Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at ..."

Yoshinobu Higami et al. (2008)

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DOI: 10.1093/IETISY/E91-D.3.690

access: closed

type: Journal Article

metadata version: 2020-04-11

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Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu:
Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools. IEICE Trans. Inf. Syst. 91-D(3): 690-699 (2008)

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