"Interconnection-Delay and Clock-Skew Estimate Modelings for ..."

Koichi Fujiwara et al. (2016)

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DOI: 10.1587/TRANSFUN.E99.A.1294

access: closed

type: Journal Article

metadata version: 2020-04-11

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Koichi Fujiwara, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa:
Interconnection-Delay and Clock-Skew Estimate Modelings for Floorplan-Driven High-Level Synthesis Targeting FPGA Designs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(7): 1294-1310 (2016)

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