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"A Low Power and High Throughput Self Synchronous FPGA Using 65 nm CMOS ..."
Benjamin Stefan Devlin et al. (2010)
- Benjamin Stefan Devlin, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
A Low Power and High Throughput Self Synchronous FPGA Using 65 nm CMOS with Throughput Optimization by Pipeline Alignment. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(7): 1319-1328 (2010)
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