"A Fast-Lock Low-Power Subranging Digital Delay-Locked Loop."

Hsin-Shu Chen, Jyun-Cheng Lin (2010)

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DOI: 10.1587/TRANSELE.E93.C.855

access: closed

type: Journal Article

metadata version: 2020-04-11

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Hsin-Shu Chen, Jyun-Cheng Lin:
A Fast-Lock Low-Power Subranging Digital Delay-Locked Loop. IEICE Trans. Electron. 93-C(6): 855-860 (2010)

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