"Chip Level Simulation of Substrate Noise Coupling and Interference in RF ..."

Naoya Azuma et al. (2014)

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DOI: 10.1587/TRANSELE.E97.C.546

access: closed

type: Journal Article

metadata version: 2023-09-30

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Naoya Azuma, Shunsuke Shimazaki, Noriyuki Miura, Makoto Nagata, Tomomitsu Kitamura, Satoru Takahashi, Motoki Murakami, Kazuaki Hori, Atsushi Nakamura, Kenta Tsukamoto, Mizuki Iwanami, Eiji Hankui, Sho Muroga, Yasushi Endo, Satoshi Tanaka, Masahiro Yamaguchi:
Chip Level Simulation of Substrate Noise Coupling and Interference in RF ICs with CMOS Digital Noise Emulator. IEICE Trans. Electron. 97-C(6): 546-556 (2014)

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