"An area-efficient dual replica-bitline delay technique for ..."

Yi Li et al. (2014)

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DOI: 10.1587/ELEX.11.20130992

access: open

type: Journal Article

metadata version: 2021-02-12

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  - https://dblp.org/rec/journals/ieiceee/LiWZCHYZ14
Yi Li, Liang Wen, Yuejun Zhang, Xu Cheng, Jun Han, Zhiyi Yu, Xiaoyang Zeng:
An area-efficient dual replica-bitline delay technique for process-variation-tolerant low voltage SRAM sense amplifier timing. IEICE Electron. Express 11(3): 20130992 (2014)

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