"Built-in jitter measurement circuit for PLL based on variable vernier ..."

Zhikuang Cai et al. (2017)

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DOI: 10.1587/ELEX.13.20161116

access: open

type: Journal Article

metadata version: 2021-02-12

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  - https://dblp.org/rec/journals/ieiceee/CaiXHY17
Zhikuang Cai, Haobo Xu, Shanwen Hu, Jun Yang:
Built-in jitter measurement circuit for PLL based on variable vernier delay line. IEICE Electron. Express 14(3): 20161116 (2017)

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