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"A High Throughput/Gate AES Hardware Architecture by Compressing Encryption ..."

Rei Ueno et al. (2016)

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DOI: —

access: open

type: Informal or Other Publication

metadata version: 2020-05-11

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  - electronic edition @ iacr.org (open access)
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  persistent URL:
  - https://dblp.org/rec/journals/iacr/UenoMHA16
Rei Ueno, Sumio Morioka, Naofumi Homma, Takafumi Aoki:
A High Throughput/Gate AES Hardware Architecture by Compressing Encryption and Decryption Datapaths - Toward Efficient CBC-Mode Implementation. IACR Cryptol. ePrint Arch. 2016: 595 (2016)

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