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"Design of INV/BUFF Logic Locking For Enhancing the Hardware Security."

Naveenkumar R et al. (2023)

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DOI: 10.1007/S10836-023-06061-Y

access: closed

type: Journal Article

metadata version: 2023-07-13

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Naveenkumar R, N. M. Sivamangai, Napolean A, S. Sridevi Sathya Priya, S. V. Ashika:
Design of INV/BUFF Logic Locking For Enhancing the Hardware Security. J. Electron. Test. 39(2): 141-153 (2023)

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