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"A DFT Technique for Testing High-Speed Circuits with Arbitrarily Slow Testers."

Muhammad Nummer, Manoj Sachdev (2003)

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DOI: 10.1023/A:1023753231177

access: closed

type: Journal Article

metadata version: 2020-09-11

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Muhammad Nummer, Manoj Sachdev:
A DFT Technique for Testing High-Speed Circuits with Arbitrarily Slow Testers. J. Electron. Test. 19(3): 299-314 (2003)

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