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"Hierarchical VLSI Fault Tracing by Successive Circuit Extraction from CAD ..."
Katsuyoshi Miura, Koji Nakamae, Hiromu Fujioka (1997)
- Katsuyoshi Miura, Koji Nakamae, Hiromu Fujioka:
Hierarchical VLSI Fault Tracing by Successive Circuit Extraction from CAD Layout Data in the CAD-Linked EB Test System. J. Electron. Test. 10(3): 255-269 (1997)
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