"A Test Time Reduction Algorithm for Test Architecture Design for ..."

Sandeep Kumar Goel, Erik Jan Marinissen (2003)

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DOI: 10.1023/A:1024644026761

access: closed

type: Journal Article

metadata version: 2024-02-05

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Sandeep Kumar Goel, Erik Jan Marinissen:
A Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips. J. Electron. Test. 19(4): 425-435 (2003)

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