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"Clock-Less DFT and BIST for Dual-Rail Asynchronous Circuits."

Tsai-Chieh Chen et al. (2021)

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DOI: 10.1007/S10836-021-05963-Z

access: closed

type: Journal Article

metadata version: 2021-12-15

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  dblp key:
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  - https://dblp.org/rec/journals/et/ChenPHTLLC21
Tsai-Chieh Chen, Chia-Cheng Pai, Yi-Zhan Hsieh, Hsiao-Yin Tseng, Chien-Mo James Li, Tsung-Te Liu, I-Wei Chiu:
Clock-Less DFT and BIST for Dual-Rail Asynchronous Circuits. J. Electron. Test. 37(4): 453-471 (2021)

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