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"The Dawn of Predictive Chip Yield Design: Along and Beyond the Memory Lane."

Rajiv V. Joshi et al. (2010)

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DOI: 10.1109/MDT.2010.95

access: closed

type: Journal Article

metadata version: 2020-05-17

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  - journals/dt/JoshiKPTC10
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  persistent URL:
  - https://dblp.org/rec/journals/dt/JoshiKPTC10
Rajiv V. Joshi, Rouwaida Kanj, Anthony Pelella, Arthur Tuminaro, Yuen H. Chan:
The Dawn of Predictive Chip Yield Design: Along and Beyond the Memory Lane. IEEE Des. Test Comput. 27(6): 36-45 (2010)

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