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"Design of Reversible Arithmetic Logic Unit with Built-In Testability."
Hari Mohan Gaur, Ashutosh Kumar Singh, Umesh Ghanekar (2019)
- Hari Mohan Gaur, Ashutosh Kumar Singh, Umesh Ghanekar:
Design of Reversible Arithmetic Logic Unit with Built-In Testability. IEEE Des. Test 36(5): 54-61 (2019)
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