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"A 1 μs Locking Time Dual Loop ADPLL with Foreground Calibration-Based ..."

Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal (2022)

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DOI: 10.1007/S00034-021-01861-Z

access: closed

type: Journal Article

metadata version: 2022-03-15

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  dblp key:
  - journals/cssp/SahaniSA22
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  - https://dblp.org/rec/journals/cssp/SahaniSA22
Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal:
A 1 μs Locking Time Dual Loop ADPLL with Foreground Calibration-Based 6 ps Resolution Flash TDC in 180 nm CMOS. Circuits Syst. Signal Process. 41(3): 1299-1323 (2022)

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