"Design of Area Efficient In-Memory Adder and Sum-Comparator with a ..."

Linknath Surya Balasubramanian et al. (2025)

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DOI: 10.1007/S00034-025-03033-9

access: closed

type: Journal Article

metadata version: 2025-08-05

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  - https://dblp.org/rec/journals/cssp/BalasubramanianRGRLYK25
Linknath Surya Balasubramanian, Elijah Racz, Anoop Gopinath, Maher E. Rizkalla, John J. Lee, Trond Ytterdal, Mukesh Kumar:
Design of Area Efficient In-Memory Adder and Sum-Comparator with a Variable Reference Voltage Mechanism. Circuits Syst. Signal Process. 44(7): 5343-5356 (2025)

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