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"Timing Error Aware Register Allocation in TS."

Sheng Xiao et al. (2022)

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DOI: 10.32604/CSSE.2022.019106

access: closed

type: Journal Article

metadata version: 2021-09-24

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  - journals/csse/XiaoHYZY22
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  - https://dblp.org/rec/journals/csse/XiaoHYZY22
Sheng Xiao, Jing He, Xi Yang, Heng Zhou, Yujie Yuan:
Timing Error Aware Register Allocation in TS. Comput. Syst. Sci. Eng. 40(1): 273-286 (2022)

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