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ORCID"PEFSL: A deployment Pipeline for Embedded Few-Shot Learning on a FPGA SoC."
Lucas Grativol Ribeiro et al. (2024)
- Lucas Grativol Ribeiro, Lubin Gauthier, Mathieu Léonardon, Jérémy Morlier, Antoine Lavrard-Meyer, Guillaume Muller, Virginie Fresse, Matthieu Arzel:
PEFSL: A deployment Pipeline for Embedded Few-Shot Learning on a FPGA SoC. CoRR abs/2404.19354 (2024)
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last updated on 2024-05-27 14:55 CEST by the dblp team
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