"Exploiting Challenges of Sub-20 nm CMOS for Affordable Technology Scaling."

Kaushik Vaidyanathan (2015)

> Home

Details and statistics

DOI: —

access: open

type: Informal or Other Publication

metadata version: 2018-08-13

- view
  - electronic edition @ arxiv.org (open access)
- export record
  dblp key:
  - journals/corr/Vaidyanathan15
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/corr/Vaidyanathan15
Kaushik Vaidyanathan:
Exploiting Challenges of Sub-20 nm CMOS for Affordable Technology Scaling. CoRR abs/1509.00885 (2015)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.