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"FPGA Based Efficient Multiplier for Image Processing Applications Using ..."

Satish S. Bhairannawar et al. (2014)

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DOI: —

access: open

type: Informal or Other Publication

metadata version: 2020-11-23

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  - electronic edition @ arxiv.org (open access)
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  dblp key:
  - journals/corr/BhairannawarRRVP14
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  persistent URL:
  - https://dblp.org/rec/journals/corr/BhairannawarRRVP14
Satish S. Bhairannawar, R. Rathan, K. B. Raja, K. R. Venugopal, Lalit M. Patnaik:
FPGA Based Efficient Multiplier for Image Processing Applications Using Recursive Error Free Mitchell Log Multiplier and KOM Architecture. CoRR abs/1407.2082 (2014)

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