"Area-efficient and high-speed hardware structure of hybrid cryptosystem ..."

Senthil Murugan Maniam, T. Sasilatha (2021)

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DOI: 10.1002/CPE.5287

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type: Journal Article

metadata version: 2021-01-26

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Senthil Murugan Maniam, T. Sasilatha:
Area-efficient and high-speed hardware structure of hybrid cryptosystem (AES-RC4) for maximizing key lifetime using parallel subpipeline architecture. Concurr. Comput. Pract. Exp. 33(3) (2021)

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