


default search action
"FPGA design of FFT based intelligent accelerator with optimized Wallace ..."
L. Malathi, A. Bharathi, A. N. Jayanthi (2024)
- L. Malathi
, A. Bharathi, A. N. Jayanthi:
FPGA design of FFT based intelligent accelerator with optimized Wallace tree multiplier for image super resolution and quality enhancement. Biomed. Signal Process. Control. 88(Part B): 105599 (2024)

manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.