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"Design Method of Vertical Lattice Loop Structure for Parasitic Inductance ..."

Si-Seok Yang et al. (2022)

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DOI: 10.1109/ACCESS.2022.3220325

access: open

type: Journal Article

metadata version: 2022-12-05

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  - https://dblp.org/rec/journals/access/YangMEKL22
Si-Seok Yang, Sung-Soo Min, Chan-Hyeok Eom, Rae-Young Kim, Gi-Young Lee:
Design Method of Vertical Lattice Loop Structure for Parasitic Inductance Reduction in a GaN HEMTs-Based Converter. IEEE Access 10: 117215-117224 (2022)

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